VHDL Codes
VHDL CODES 4:1 MUX USING IF ELSE STATEMENT library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity MUX41 is Port ( I : in STD_LOGIC_VECTOR (03 downto 0); SEL : in STD_LOGIC_VECTOR (01 downto 0); Y : out STD_LOGIC); end MUX41; architecture Behavioral of MUX41 is begin PROCESS (I,SEL) BEGIN IF(SEL="00")THEN Y<=I(0); ELSIF(SEL="01")THEN Y<=I(1); ELSIF(SEL="10")THEN Y<=I(2); ELSE Y<=I(3); END IF; END PROCESS; end Behavioral; 2. 4:1 MUX ...