Tuesday, August 25, 2015

VHDL Codes

VHDL CODES     
  1.   4:1 MUX USING IF ELSE STATEMENT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

 entity MUX41 is
   Port ( I : in  STD_LOGIC_VECTOR (03 downto 0);
          SEL : in  STD_LOGIC_VECTOR (01 downto 0);
          Y : out  STD_LOGIC);
end MUX41;
architecture Behavioral of MUX41 is
begin
PROCESS (I,SEL)
BEGIN
IF(SEL="00")THEN
Y<=I(0);
ELSIF(SEL="01")THEN
Y<=I(1);
ELSIF(SEL="10")THEN
Y<=I(2);
ELSE
Y<=I(3);
END IF;
END PROCESS;
end Behavioral;
 
2.         4:1 MUX USING CASE STATEMENT 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux41 is
   Port ( I0 : in  STD_LOGIC;
          I1 : in  STD_LOGIC;
          I2 : in  STD_LOGIC;
          I3 : in  STD_LOGIC;
          SEL : in  STD_LOGIC_VECTOR (01 downto 0);
          Y : out  STD_LOGIC);
end mux41;
architecture Behavioral of mux41 is
begin
PROCESS (I0,I1,I2,I3,SEL)
BEGIN
CASE SEL IS
WHEN "00"=>Y<=I0;
WHEN "01"=>Y<=I1;
WHEN "10"=>Y<=I2;
WHEN OTHERS=>Y<=I3;
END CASE;
END PROCESS;
end Behavioral;
3.            3:8 DECODER USING CASE STATEMENT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dec38 is
   Port ( a : in  STD_LOGIC;
          b : in  STD_LOGIC;
          c : in  STD_LOGIC;
          d : out  STD_LOGIC_VECTOR (07 downto 0));
end dec38;
architecture Behavioral of dec38 is
signal enw:std_logic_vector(2 downto 0);
begin
enw<=a & b & c;
process(enw)
begin
case enw is
when"000"=>d<="00000001";
when"001"=>d<="00000010";
when"010"=>d<="00000100";
when"011"=>d<="00001000";
when"100"=>d<="00010000";
when"101"=>d<="00100000";
when"110"=>d<="01000000";
when"111"=>d<="10000000";
when others=>d<="00000000";
end case;

 
 
 
 
 
 

Wednesday, July 22, 2015

Learn VHDL programming ONLINE!!!

      To learn VHDL programming just go through these websites ...Have fun

You will get the programs too.  

1.http://esd.cs.ucr.edu/labs/tutorial/

2.http://www.asic-world.com/vhdl/tutorial.html

3.http://users.ece.gatech.edu/sudha/book/starters-guide/


Thursday, April 23, 2015

Simple Temperature controller

Simple Temperature controller mini project using IC741 used as comparator!
Circuit diagram:
Above circuit consist of ic741 which is used as comparaotor.The reference temp. is given at inverting terminal of 741 which is adjusted by potentiometer so that can have the ref.temp. which you want.

Thursday, March 19, 2015

Sunday, March 15, 2015

Logic Gates using OP-AMP

Building Logic gates using Op-amp 
1.AND gate using op-amp:circuit diagram
Check out the above circuit
At inverting input of opamp a reference voltage of 3.75 is given which is approximately 3/4th of Logic 1 i.e 5V
So that it can operate well like AND logic.

Monday, March 9, 2015

Code lock system

Code lock system:Simple project
 
 
When you make on the buttons 1,3and 6 the lock will open the relay will be driven and you can drive your load whichever is connected to the relay circuit.
Its implemented and tested in PROTEUS simulation software.
Have a fun with this simple lock system.

Some useful parameters

Dielectric constant  Metals have infinite Dielectric constant  As usually metals permittivity is very large than of free space hence its Die...