TRONIX FUNDA

VHDL CODES          4:1 MUX USING IF ELSE STATEMENT library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;   ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;   entity MUX41 is    Port ( I : in  STD_LOGIC_VECTOR (03 downto 0);           SEL : in  STD_LOGIC_VECTOR (01 downto 0);           Y : out  STD_LOGIC); end MUX41; architecture Behavioral of MUX41 is begin PROCESS (I,SEL) BEGIN IF(SEL="00")THEN Y<=I(0); ELSIF(SEL="01")THEN Y<=I(1); ELSIF(SEL="10")THEN Y<=I(2); ELSE Y<=I(3); END IF; END PROCESS; end Behavioral;   2.         4:1 MUX ...

      To learn VHDL programming just go through these websites ...Have fun You will get the programs too.   1.http://esd.cs.ucr.edu/labs/tutorial/ 2.http://www.asic-world.com/vhdl/tutorial.html 3.http://users.ece.gatech.edu/sudha/book/starters-guide/

Simple Temperature controller mini project using IC741 used as comparator! Circuit diagram: Above circuit consist of ic741 which is used as comparaotor.The reference temp. is given at inverting terminal of 741 which is adjusted by potentiometer so that can have the ref.temp. which you want.

Op-amp virtual ground and virtual short concept  

Building Logic gates using Op-amp   1.AND gate using op-amp:circuit diagram Check out the above circuit At inverting input of opamp a reference voltage of 3.75 is given which is approximately 3/4th of Logic 1 i.e 5V So that it can operate well like AND logic.

Code lock system:Simple project     When you make on the buttons 1,3and 6 the lock will open the relay will be driven and you can drive your load whichever is connected to the relay circuit. Its implemented and tested in PROTEUS simulation software. Have a fun with this simple lock system.